India’s Chip-Design Pipeline Accelerates as C2S Trains 68,000 and Enables 254 Semiconductor Tape-Outs

India’s semiconductor design ecosystem is expanding rapidly under the government’s Chips to Start-ups (C2S) Programme, which has now trained more than 68,000 students and enabled 254 semiconductor designs to reach the tape-out stage. The programme is helping Indian universities move beyond classroom-level chip design towards actual fabrication and prototype development.

Implemented by the Ministry of Electronics and Information Technology, C2S aims to create 85,000 industry-ready professionals at the B.Tech, M.Tech and PhD levels. The initiative addresses two major challenges facing India’s semiconductor ambitions: the shortage of skilled chip designers and limited access to the expensive software and fabrication infrastructure required to turn semiconductor concepts into working silicon.

Of the 254 designs taped out so far, 175 have been processed at the 180-nanometre technology node at Semiconductor Laboratory, Mohali, while another 79 have gone to overseas foundries. Tape-out represents a crucial stage in semiconductor development because it marks the point at which a completed circuit design is sent for physical fabrication.

C2S has also provided 332 academic institutions with access to professional Electronic Design Automation tools used by the global semiconductor industry. These include platforms from Synopsys, Cadence, Siemens EDA, Ansys, Keysight and AMD-Xilinx, allowing students and researchers to work with tools similar to those used by commercial chip-design companies.

From RISC-V to Neuromorphic Computing

The programme is increasingly supporting research in strategically important semiconductor technologies.

At IIT Tirupati, researchers are developing a secure RISC-V processor for cryptographic applications, combining the open RISC-V instruction-set architecture with hardware-level security capabilities.

Researchers at IIITDM Kurnool are developing a hardware accelerator intended to improve computing performance for high-performance computing and cyber-physical systems. Such specialised accelerators can perform selected workloads more efficiently than relying entirely on general-purpose processors.

At NIT Andhra Pradesh, work is underway on an energy-efficient neuromorphic processor for edge Internet of Things applications. Neuromorphic processors attempt to reproduce some characteristics of biological neural networks in hardware, allowing AI workloads to operate with significantly lower power consumption.

Meanwhile, Shri Vishnu Engineering College for Women at Bhimavaram is developing a memory-efficient co-processing unit aimed at edge-AI applications. These projects are at different stages of development and could move towards prototype validation and semiconductor fabrication as they mature.

More Designs Move Towards Fabrication

The pipeline continues to grow. Under the seventh Multi-Project Wafer shuttle organised through the ChipIN Centre, 29 additional designs were submitted for fabrication at SCL Mohali’s 180-nm process in July 2026.

Among them is an e-Passport and e-Aadhaar chip developed by IIT Bombay, along with encryption hardware, RSA modules, FFT processors, an RF power amplifier and other specialised integrated circuits from Indian academic institutions.

Multi-Project Wafer fabrication allows several independent chip designs to share the same semiconductor wafer, significantly reducing the cost of producing small quantities of experimental chips. This makes it particularly useful for university research and early-stage semiconductor development.

Building India’s Semiconductor Talent Base

India’s semiconductor strategy extends beyond constructing fabrication plants. A domestic semiconductor industry also requires engineers capable of designing processors, communication chips, power devices, sensors and specialised accelerators.

The C2S programme is attempting to build that talent base while giving students practical experience with the complete design cycle — from architecture and circuit design to verification and eventual fabrication.

The growing number of tape-outs is particularly significant because it demonstrates a shift from theoretical semiconductor education towards working silicon produced from designs created in Indian institutions.

The 180-nm process available at SCL Mohali is a mature semiconductor node rather than a leading-edge manufacturing technology. However, such nodes remain useful for a wide range of applications including analogue circuits, embedded controllers, secure electronics, sensors and research prototypes.

India’s emerging semiconductor ecosystem will ultimately require both advanced fabrication capacity and a large domestic design workforce. With more than 68,000 students trained, 254 designs already reaching tape-out and another generation of RISC-V, AI and specialised computing chips moving through development, C2S is steadily building the design side of that ecosystem.

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